Radecka, Katarzyna. <br/><br/>
Verification by error modeling  using testing techniques in hardware verification /  [electronic resource] : 
written by Katarzyna Radecka, Zeljko Zilic. 
 - Boston :  Kluwer Academic Publishers,  2003. 
 - xiv, 216 p. :  ill. 
 - Frontiers in electronic testing ;  25 .
 - Frontiers in electronic testing ;  25. .
<br/><br/>Includes bibliographical references and index. 
<br/><br/><br/>Electronic reproduction. <br/>Palo Alto, Calif. : <br/>ebrary, <br/>2013. <br/>Available via World Wide Web. <br/>Access may be limited to ebrary affiliated libraries. 
<br/><br/><label>ISBN: </label>
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration--Computer-aided design.<br/>Integrated circuits--Verification.<br/>Error analysis (Mathematics)
<br/><br/><label>Index Terms--Genre/Form: </label><br/>Electronic books.
<br/><br/><label>LC Class. No.: </label>TK7874.75  / .R33 2003eb 
<br/><br/><label>Dewey Class. No.: </label>621.39/5