Verification by error modeling [electronic resource] : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.

By: Contributor(s): Material type: TextTextSeries: Frontiers in electronic testing ; 25.Publication details: Boston : Kluwer Academic Publishers, 2003.Description: xiv, 216 p. : illSubject(s): Genre/Form: DDC classification:
  • 621.39/5 22
LOC classification:
  • TK7874.75 .R33 2003eb
Online resources:
Tags from this library: No tags from this library for this title. Log in to add tags.
Star ratings
    Average rating: 0.0 (0 votes)
No physical items for this record

Includes bibliographical references and index.

Electronic reproduction. Palo Alto, Calif. : ebrary, 2013. Available via World Wide Web. Access may be limited to ebrary affiliated libraries.

There are no comments on this title.

to post a comment.