000 03112nam a22003855i 4500
001 978-1-4302-5927-5
003 DE-He213
005 20180131132525.0
007 cr nn 008mamaa
008 130926s2013 xxu| s |||| 0|eng d
020 _a9781430259275
_9978-1-4302-5927-5
024 7 _a10.1007/978-1-4302-5927-5
_2doi
050 4 _aQA75.5-76.95
072 7 _aUY
_2bicssc
072 7 _aCOM014000
_2bisacsh
082 0 4 _a004
_223
100 1 _aRahman, Rezaur.
_eauthor.
245 1 0 _aIntel® Xeon Phi™ Coprocessor Architecture and Tools
_h[electronic resource] :
_bThe Guide for Application Developers /
_cby Rezaur Rahman.
264 1 _aBerkeley, CA :
_bApress :
_bImprint: Apress,
_c2013.
300 _aXXI, 232 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
506 0 _aOpen Access
520 _aIntel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor. Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them. In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.
650 0 _aComputer science.
650 1 4 _aComputer Science.
650 2 4 _aComputer Science, general.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781430259268
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4302-5927-5
912 _aZDB-2-CWD
999 _c188794
_d188794